1. Field
The present disclosure relates to a switching power supply circuit and power factor correction circuit that convert an alternating current input voltage to a predetermined direct current output voltage and supply the output voltage to a load, and in particular, relates to a switching power supply circuit and power factor correction circuit such that switching can be carried out between a critical conduction control method and a continuous conduction control method.
2. Related Art
A switching power supply circuit is used in many electronic instruments to which a commercial alternating current power supply (100V to 240V AC) is supplied in order to obtain a direct current power supply that drives an internal electronic circuit. Therefore, a rectifier circuit that converts a commercial alternating current power supply to direct current is needed in the switching power supply circuit. A rectifier circuit has a problem in that current flows into a smoothing capacitor connected to a latter stage of the rectifier circuit only when the input voltage reaches the vicinity of a peak exceeding the voltage of the smoothing capacitor, because of which a high frequency current component is generated, forming a high frequency noise source, and the power factor decreases.
The power factor is a value that is the input effective power, which is the time average of the product of the input voltage and input current in an alternating current circuit, divided by the apparent power, which is the product of the effective value of the input voltage and the effective value of the input current, wherein the effective power is obtained by multiplying a coefficient (power factor) determined by the load by the apparent power. When a simple resistance load is connected to a 100 volt (V) alternating current, the voltage waveform and current waveform are in phase, and the power factor is 1. However, a switching power supply is such that the current phase deviates from the voltage phase due to load factors other than resistance, such as a capacitor or choke coil. In this case, it is necessary to increase the input current in order to compensate for the power factor decreasing by an amount commensurate with the deviation, which increases the power loss in the input line leading to the rectifier circuit. Therefore, it is necessary to prevent a decrease in power factor, thereby suppressing power loss, and to restrict the high frequency noise, using a power factor correction (PFC) circuit.
Broadly speaking, there are two methods of controlling a power factor correction circuit, those being a continuous conduction control method and a critical conduction control method. A critical conduction control method is a control method whereby the timing at which an inductor current flowing through an inductor becomes zero is detected, and a switching element is turned on at that timing. The critical conduction control method is such that, as a switching element is turned on by an inductor current reaching zero being detected, soft switching can be realized, turn-on loss is smaller than in the case of the continuous conduction control method, which involves hard switching, and efficiency is good. However, the critical conduction control method is such that the peak value of the inductor current is higher than the peak value in the case of the continuous conduction control method, and it is necessary to increase the inductor current capacity. Therefore, the critical conduction control method is characterized by being used in a power factor correction circuit of a switching power supply circuit with low power consumption in the region of, for example, 250 watts (W) or less, but not being appropriate to a power factor correction circuit of a switching power supply circuit of a larger capacity.
A power factor correction circuit is a circuit that corrects in such a way as to bring the power factor closer to 1 in a switching power supply circuit by bringing an alternating current input current waveform in phase with an alternating current input voltage waveform rectified by a rectifier circuit. Furthermore, the power factor correction circuit restricts the generation of harmful electro-magnetic interference (EMI) and high frequency current or voltage that leads to instrument destruction.
The continuous conduction control method and critical conduction control method have separate characteristics, but a power factor correction circuit wherein the heretofore described problems are addressed by the two methods being combined is known (for example, refer to Japanese Patent Application No. 2013-509141). The power factor correction circuit shown in 2013-509141 operates by switching between the critical conduction control method and continuous conduction control method when there is a heavy load.
FIG. 8 is a circuit diagram showing a switching power supply circuit in which is used a power factor correction circuit wherein switching between a critical conduction control method and continuous conduction control method can be carried out. In the following description, the same reference sign may be used for a terminal name and the voltage, a signal, and the like, of the terminal.
In the switching power supply circuit of FIG. 8, an alternating current input voltage is full-wave rectified by a full-wave rectifier circuit 1, one end of a capacitor 2 is connected to an output port of the full-wave rectifier circuit 1, and a high frequency component caused by a switching operation of a switching element 4, to be described hereafter, is removed by the capacitor 2. Furthermore, a step-up circuit including an inductor 3, the switching element 4 formed of a metal-oxide-semiconductor field effect transistor (MOSFET), a diode 5, and a capacitor 6 is connected to the output port of the full-wave rectifier circuit 1. By rectified voltage output from the full-wave rectifier circuit 1 being boosted and rectified by the step-up circuit, a direct current output voltage of, for example, approximately 400V can be supplied to a load (not shown) connected between a power supply output terminal 7 and the ground.
A power factor correction circuit 100 is configured of an integrated circuit wherein various kinds of function are integrated, and corrects a power factor by causing the inductor current and input voltage in the step-up circuit to be in-phase.
The power factor correction circuit 100 has an FB terminal, an IS terminal, an OUT terminal, an RT terminal, and a COMP terminal as external connection terminals. The FB terminal is a terminal for inputting a feedback signal that feeds back output voltage. The IS terminal, a current detecting resistor R3 being connected between the IS terminal and the ground, is a terminal for converting current flowing into the switching element 4 into negative voltage and detecting current flowing into the inductor 3. The OUT terminal is a terminal for the gate drive output of the MOSFET configuring the switching element 4, and controls the turning on and turning off of the MOSFET. The RT terminal, a timing resistor R1 of which one end is connected to the ground being connected thereto, is a terminal for connecting a resistor that determines an oscillation waveform, and is a terminal for generating a sawtooth foam oscillation output having an inclination in accordance with the resistance value of the timing resistor R1. The COMP terminal is a terminal for connecting a phase compensation element, and is connected to the ground via a capacitor C1, and a series circuit of a resistor R6 and a capacitor C2 is connected in parallel to the capacitor C1. The capacitors C1 and C2 and resistor R6 configure a phase compensation circuit. Additionally, an unshown power supply voltage input VCC terminal, an unshown ground connection GND terminal, and the like, are included in the power factor correction circuit 100.
An error amplifier 11, which amplifies and outputs the difference between the detected value of output voltage input into the FB terminal and a reference voltage Vref, and a pulse width modulation (PWM) comparator 12 are provided in the interior of the power factor correction circuit 100. The power factor correction circuit 100 also has an oscillator 13, a level conversion circuit 20, a continuous conduction control setting circuit 30, a zero current detection (ZCD) comparator 16, OR circuits 14a and 14b, and an RS flip-flop 15. The power factor correction circuit 100 further has an overvoltage protection (OVP) comparator 18 for protecting against overvoltage, and an overcurrent protection (OCP) comparator 19 for detecting an overcurrent.
The drain terminal of the switching element 4 is connected to a connection point of the inductor 3 and diode 5, while the source terminal is connected to the ground of the power factor correction circuit 100. The power supply output terminal 7 is connected to the ground via serially connected resistors R4 and R5, and a connection point of the resistors R4 and R5 is connected to the FB terminal.
The switching power supply circuit with the heretofore described configuration is such that the power factor is corrected by causing the inductor current and input voltage in the step-up circuit to be in-phase by the power factor correction circuit 100. Hereafter, details of an operation of the switching power supply circuit will be described.
In the power factor correction circuit 100, the error amplifier 11 is formed of a transconductance amplifier, and receives the reference voltage Vref in a non-inverting input terminal thereof, while the FB terminal is connected to an inverting input terminal. Therefore, the power factor correction circuit 100 controls so that the voltage of the FB terminal becomes equal to the reference voltage Vref. The voltage of the power supply output terminal 7 divided by the resistors R4 and R5 is input into the FB terminal. The output of the error amplifier 11 is connected to the COMP terminal and an inverting input terminal of the PWM comparator 12.
The capacitor C1, resistor R6, and capacitor C2 for configuring the phase compensation circuit are connected to the COMP terminal, and smooth a ripple component corresponding to a change in the alternating current input voltage.
The output waveform of the oscillator 13 is input into a non-inverting input terminal of the PWM comparator 12. The oscillator 13 is connected to the external timing resistor R1 via the RT terminal, from which a constant voltage is output, and generates a sawtooth form oscillation output having an inclination in accordance with the timing resistor R1 by charging a built-in capacitor, with the value of current flowing in accordance with the resistance value of the timing resistor R1 as a reference. When the output waveform of the oscillator 13 exceeds the voltage of the COMP terminal, the output of the PWM comparator 12 outputs a reset signal to the RS flip-flop 15 via the OR circuit 14a. Therefore, an OUT terminal of the RS flip-flop 15 switches to a low (L) level, whereby the switching element 4 is switched to a turned off state.
Furthermore, the outputs of the OVP comparator 18 for protection against overvoltage and the OCP comparator 19 for protection against overcurrent are connected to the OR circuit 14a. 
The OVP comparator 18 for protection against overvoltage receives a reference voltage Vovp in an inverting input terminal side, while the FB terminal is connected to a non-inverting input terminal side. When the FB terminal voltage, in which the power supply output voltage is reflected, exceeds the reference voltage Vovp, the output of the OVP comparator 18 for protection against overvoltage switches to a high (H) level, thereby resetting the RS flip-flop 15.
Also, the OCP comparator 19 for protection against overcurrent receives a reference voltage Vocp in a non-inverting input terminal side, while the level conversion circuit 20 connected to the IS terminal is connected to an inverting input terminal side, whereby the OCP comparator 19 receives a second current level signal S2. The output of the OCP comparator 19 for protection against overcurrent is connected to a reset terminal of the RS flip-flop 15 via the OR circuit 14a, and outputs at an H level when the second current level signal S2 is lower than the reference voltage Vocp, thereby resetting the RS flip-flop 15. The second current level signal S2 is a signal that decreases further the greater the current flowing into the resistor R3, as will be described hereafter.
First to third current level signals S1, S2, and S3 output from the level conversion circuit 20 connected to the IS terminal are such that signals of differing values of voltage between a reference voltage Vref2 and the IS terminal being resistively divided are output. The first and second current level signals S1 and S2 of the level conversion circuit 20 are input into the continuous conduction control setting circuit 30, and the continuous conduction control setting circuit 30 generates a second set pulse S8 (a continuous conduction control turn-on signal) supplied to the RS flip-flop 15 via the OR circuit 14b. 
Also, an output signal of the ZCD comparator 16, to which the third current level signal S3 is supplied, is input via the OR circuit 14b into a set terminal of the RS flip-flop 15 as a first set pulse, which is a critical conduction control turn-on signal. Generation of the first to third current level signals S1, S2, and S3 and the second set pulse S8 signal will be illustrated hereafter in FIG. 9.
The first set pulse, which is the output signal of the ZCD comparator 16, and the second set pulse S8 are input into the OR circuit 14b, and the OR circuit 14b sets the RS flip-flop 15 at the timing of whichever of the signals reaches the H level first, thereby switching the OUT terminal to a turn-on state H level.
FIG. 9 is a circuit diagram showing a specific configuration of the level conversion circuit and continuous conduction control setting circuit configuring the power factor correction circuit.
As shown in FIG. 9, the level conversion circuit 20 is configured of four resistors R21 to R24 connected in series, wherein one end is connected to the positive reference voltage Vref2, while the other end is connected to the IS terminal. The current detecting resistor R3 configuring an inductor current detector circuit is connected to the IS terminal, and when current flows into the current detecting resistor R3, the detected voltage of an inductor current of negative voltage, whose inductor current has been detected, is supplied.
In the level conversion circuit 20, input voltage from the IS terminal is shifted to a positive voltage side of polarity the reverse that of the detected voltage of the inductor current. Therefore, the level conversion circuit 20 converts the inductor current flowing into the inductor 3 into the first to third current level signals S1, S2, and S3 proportional to the inductor current, and outputs the first to third current level signals S1, S2, and S3 at mutually differing voltage levels. Herein, “proportional” is used to mean that the output is a linear function of the input.
The first current level signal S1 is output from a connection point of the resistors R21 and R22 on the reference voltage Vref2 side, and supplied to the continuous conduction control setting circuit 30. Also, the second current level signal S2 is output from a connection point of the intermediate resistors R22 and R23, and supplied to each of the OCP comparator 19 for protection against overcurrent and continuous conduction control setting circuit 30 of the power factor correction circuit 100. Furthermore, the third current level signal S3 is output from a connection point of the resistors R23 and R24 on the IS terminal side, and supplied to the ZCD comparator 16 of the power factor correction circuit 100.
The ZCD comparator 16 functions as a zero current detector circuit that detects the current flowing into the inductor 3 reaching zero by comparing the third current level signal 3 with a reference voltage Vzcd.
As shown in FIG. 9, the continuous conduction control setting circuit 30 includes a peak hold circuit 40 and a set pulse generator circuit 50, wherein the second set pulse S8 generated in the set pulse generator circuit 50 is output to the OR circuit 14b shown in FIG. 8.
The second set pulse S8 functions so as to change the turn-on timing of the switching element 4 in response to a heavy load to the timing at which a zero current is detected or earlier, and switch the control method from critical conduction control to continuous conduction control when there is a heavy load.
In the continuous conduction control setting circuit 30, an output signal S0 of the RS flip-flop 15 shown in FIG. 8 and the first current level signal S1 of the level conversion circuit 20 are input into the peak hold circuit 40. Further, a peak level signal S6 is generated from the first current level signal S1 in the peak hold circuit 40, and the second set pulse S8, which regulates the turn-on timing of the switching element 4, is generated in the set pulse generator circuit 50.
The peak hold circuit 40 includes a one-shot circuit 41, a transfer gate 42, and a hold circuit 43. The one-shot circuit 41 has a MOSFET 31, a constant current supply 32, a capacitor C4, inverters 33 and 34, a NAND circuit 35, and an inverter 36, and generates one-shot pulses S4 and S5 in synchronization with the turn-off timing of the switching element 4. In the peak hold circuit 40, the output signal S0 of the RS flip-flop 15 is supplied to a gate terminal of the MOSFET 31, whereby the MOSFET 31 is turned on and off. Therefore, the capacitor C4 connected in parallel to the MOSFET 31 operates so as to repeat discharge by the MOSFET 31 and charging by the constant current supply 32. The output signal S0 of the RS flip-flop 15 is input into the inverter 33, and an input terminal of the inverter 34 is connected to a connection point of the capacitor C4 and constant current supply 32, whereby a charge voltage of the capacitor C4 is supplied. The output voltages of the two inverters 33 and 34 are both input into the NAND circuit 35, whereby the one-shot pulse S4 is generated. Furthermore, the one-shot pulse S4 generated in the NAND circuit 35 is inverted in the inverter 36, whereby one more reverse phase one-shot pulse S5 is generated.
The one-shot pulses S4 and S5 are supplied to an inverting input terminal and non-inverting input terminal respectively of the transfer gate 42. Herein, when the one-shot pulse S4 is at an L level and the one-shot pulse S5 is at an H level, the transfer gate 42 is in an on (conductive) state.
The hold circuit 43 is configured of a circuit wherein a resistor R7 and capacitor C3 are connected in series, holds the first current level signal S1 of the level conversion circuit 20 when the transfer gate 42 is in an on-state, and outputs the peak level signal S6.
The set pulse generator circuit 50 has an amplifier circuit (voltage follower) S1, a resistance circuit wherein two resistors R8 and R9 are connected in series, and a comparator circuit 52. The amplifier circuit 51 carries out impedance conversion of the peak level signal S6 generated in the peak hold circuit 40, and an output terminal thereof is connected via the resistors R8 and R9 to GND. Therefore, the amplifier circuit 51 outputs voltage equal to the peak level signal S6, and the voltage is divided by the resistors R8 and R9, whereby a reference voltage signal S7 is generated. The reference voltage signal S7 is supplied to an inverting input terminal of the comparator circuit 52, the second current level signal S2 is supplied from the level conversion circuit 20 to a non-inverting terminal, and the comparator circuit 52 compares the second current level signal S2 with the voltage level of the reference voltage signal S7. When the second current level signal S2 reaches a voltage exceeding the reference voltage signal S7, the comparator circuit 52 outputs the second set pulse S8, which is input via the OR circuit 14b into the set terminal of the RS flip-flop 15.
FIG. 10 is a timing diagram showing main portion signal waveforms of the one-shot circuit configuring the continuous conduction control setting circuit.
The one-shot circuit 41 is such that the output signal S0 of the RS flip-flop 15 is supplied, the output signal S0 is at an L level from a time t0 or earlier until a time t1, and the MOSFET 31 is in an off-state, as is the switching element 4. At this time, a charge current from the constant current supply 32 is flowing into the capacitor C4, because of which the capacitor C4 has already been charged to a predetermined voltage level (H level) at the time t0. Therefore, an H level is output from the inverter 33, into which the output signal S0 is input, to the NAND circuit 35 during the period from the time t0 to t1, while an L level is output to the NAND circuit 35 from the inverter 34. Therefore, the NAND circuit 35 outputs at an H level while the inverter 36 outputs at an L level, because of which the transfer gate 42 is in an off (interrupted) state.
Next, on the output signal S0 switching to an H level at the time t1, the MOSFET 31 is turned on, because of which the capacitor 4 is discharged, the input to the inverter 34 is immediately inverted to an L level, and the output signals of the two inverters 33 and 34 are also simultaneously inverted to L and H levels respectively. Despite this, the output of the NAND circuit 35 is held at the H level, because of which no change occurs in the off-state of the transfer gate 42.
Next, at a time t2 at which the output signal S0 returns to the L level, the inverter 33 immediately outputs at the H level. However, the input of the inverter 34 is such that, as the charge current from the constant current supply 32 only starts to flow into the capacitor C4, the output of the inverter 34 continues at the H level state. Therefore, the output of the NAND circuit 35 inverts from the H level to the L level, and the output of the inverter 36 inverts from the L level to the H level. Therefore, the one-shot circuit 41 is such that the one-shot pulses S4 and S5, at the L level and H level respectively, are input into the transfer gate 42.
In this way, the transfer gate 42 is in a conductive state in a period from the time t2 to a time t3 because of the one-shot pulses S4 and S5 generated as mutually complementary signals in the one-shot circuit 41, and the first current level signal S1 is input into the hold circuit 43.
In the hold circuit 43, the first current level signal S1 input via the transfer gate 42 is held as the peak level signal S6 in the capacitor C3. That is, the inductor current continues to increase while the switching element 4 is in an on-state, because of which the inductor current reaches a maximum value at the moment the switching element 4 is turned off, and the one-shot pulses S4 and S5 from the one-shot circuit 41 are generated immediately after the switching element 4 is turned off.
Consequently, the peak level signal S6, wherein the peak value of the first current level signal S1 corresponding to the peak value of the inductor current is sampled and held, is held in the hold circuit 43.
The one-shot circuit 41 is such that, when the time t3 is reached and the capacitor C4 is charged by the constant current supply 32 to exceed a threshold voltage Vth of the inverter 34, the output state of the inverter 34 inverts to the L level, the output of the NAND circuit 35 inverts from the L level to the H level, and the output of the inverter 36 inverts from the H level to the L level. Therefore, the transfer gate 42 switches to an off-state. That is, the pulse widths of the one-shot pulses S4 and S5 are regulated in the period from the time t2 to the time t3.
The period from the time t2 to the time t3 is shown to be fairly long in FIG. 10 for ease of understanding, but is actually set to as short a time as possible within a range in which the sampling and holding operation can be carried out.
FIGS. 11A and 11B are timing diagrams showing main portion signal waveforms of the continuous conduction control setting circuit, wherein FIG. 11A shows an operation waveform of the peak hold circuit, while FIG. 11B shows an operation waveform of the set pulse generator circuit.
FIG. 11A shows the output signal S0 input into the peak hold circuit 40, the one-shot pulse S5 formed at the timing at which the output signal S0 falls, the first current level signal S1, and the peak level signal S6 generated from the first current level signal S1.
As previously described, when inductor current flows into the current detecting resistor R3, the current detecting resistor R3 generates a negative inductor current detection voltage, and supplies the voltage to the IS terminal. Further, as the absolute value of the inductor current detection voltage increases further the greater the inductor current, the first current level signal S1 exhibits a characteristic of extending further to the lower side of FIG. 11A the greater the inductor current. Consequently, the lower the bottom peak value of the first current level signal S1 and peak level signal S6 shown in FIG. 11A, the greater the peak value of the inductor current in each switching cycle.
Also, as heretofore described, the power factor correction circuit 100 brings an alternating current input current waveform in the switching power supply circuit in phase with an alternating current input voltage waveform after rectification, because of which the waveform of the peak level signal S6 is practically the same as the alternating current input voltage waveform after rectification. That is, when there is a heavy load and a large amount of current flows into the switching element 4 and inductor 3, the peak level signal 6 generated from the first current level signal S1 changes with greater curvature.
FIG. 11B shows the reference voltage signal S7 and second current level signal S2 input into the comparator 52 as operation waveforms of the set pulse generator circuit 50, and the second set pulse S8 output from the set pulse generator circuit 50 as a comparison output in the comparator circuit 52.
The voltage levels of the reference voltage signal S7, which changes practically in phase with the alternating current input voltage after rectification, and second current level signal S2 are compared in the set pulse generator circuit 50. The reference voltage signal S7, which is a signal wherein the peak level signal S6 output from the peak hold circuit 40 is level-shifted (divided), as heretofore described, changes with greater curvature when there is a heavy load. Also, the second current level signal S2 changes in proportion to the inductor current flowing into the inductor 3, in the same way as the first current level signal S1, and differs from the first current level signal S1 only in voltage level.
When the second current level signal S2 rises and becomes equal to the reference voltage signal S7 in accompaniment to the switching element 4 being turned off and the inductor current decreasing, the second set pulse S8, which regulates the turn-on timing of the switching element 4, is output from the comparator circuit 52.
FIGS. 12A and 12B are diagrams showing signal waveforms of an operation of the power factor correction circuit, wherein FIG. 12A shows signal waveforms of a critical operation when there is a light load, while FIG. 12B shows signal waveforms of a continuous operation when there is a heavy load.
Herein, FIGS. 12A and 12B both show, with the alternating current input voltage waveform of the alternating current power supply as a reference, the inductor current waveform, the reference voltage signal S7 that changes practically in phase with the alternating current input voltage waveform, the voltage waveform of the inductor current detection voltage input into the IS terminal of the power factor correction circuit 100, and the voltage waveform of a signal output from the OUT terminal. The voltage waveform of the signal output from the OUT terminal in the diagram is such that the pulse width has no meaning, but the pulse interval is meaningful. The second current level signal S2 (the zero current detection level) when the inductor current reaches zero, that is, a value that is the top peak value of the inductor current detection voltage waveform in FIG. 12A after level shifting, is of the constant size shown below, regardless of the size of the load.
When Vzero=Vref2·(R23+R24)/(R21+R22+R23+R24), the bottom peak value of the inductor current detection voltage waveform when there is a light load is a negative voltage with a small absolute value, because of which the bottom of the waveform of the reference voltage signal S7 is positioned to the upper side of that in FIG. 12B, and the minimum value of the reference voltage signal S7 is greater than the zero current detection level. Consequently, when there is a light load, no second set pulse S8 is output, and the switching element 4 is turned on at the timing at which the ZCD comparator 16 detects that the inductor current is zero and outputs the first set pulse. In this case, the switching element 4 changes from an off-state to an on-state at the timing at which the inductor current becomes zero, because of which the power factor correction circuit 100 operates using the critical conduction control method.
Meanwhile, when the load is heavier, the reference voltage signal S7 is displaced downward with a large curvature, as shown in FIG. 12B, and at the point at which one portion of the reference voltage signal S7 becomes lower than the zero current detection level, the second set pulse S8 is output ahead of the first set pulse from the ZCD comparator 16. Therefore, the power factor correction circuit 100 is such that the control method switches from critical conduction control to continuous conduction control when there is a heavy load.
FIG. 13 is a diagram showing waveforms of the inductor current flowing in the switching power supply circuit when there is a heavy load.
FIG. 13 shows an envelope to which the maximum value of the inductor current is connected and an envelope to which the minimum value is connected. As illustrated in FIGS. 12A and 12B, the existing power factor correction circuit 100 is such that the size of the load is determined using the inductor current detection voltage, and switching between the critical conduction control method and continuous conduction control method is carried out. Therefore, it is seen that the critical conduction control method is used in a region in which the momentary value of the envelope waveform to which is connected the maximum value of the inductor current, which changes practically in phase with the alternating current input voltage waveform, is small (that is, an intermediate region between a time t11 and a time t12, and an intermediate region between the time t12 and a time t13), while the continuous conduction control method is used in a region in which the momentary value of the envelope waveform to which the maximum value is connected is large.
The previously described power factor correction circuit 100 is such that when the power supply output voltage is constant at 400V, the average value of the inductor current that oscillates up and down is proportional to the supply power of one switching cycle. Therefore, even in the case of an inductor of the same size as in the case of the existing critical conduction control, the power that can be supplied to the load under the same maximum peak current value condition can be set high by switching from the critical conduction control method to the continuous conduction control method when there is a heavy load, whereby a predetermined direct current voltage can be supplied to a greater load. Also, from a different viewpoint, when supplying the same power to the load, the same power can be supplied using continuous conduction control in a state lower than the peak current when using critical conduction control.